//Context
Most RFIDs are manufactured on older technology nodes. This translates as less transistors per square area and more voltage to switch the transistors compared to a newer technology. The tags work on wireless power scavenged from the reader. RFIDs have severe area and power constraints. This leaves area and power just enough to run the most critical applications on the tag. Since the transactions between the reader and the RFID tag are wireless, they may be more prone to malicious attacks. For sensitive applications like contact-less credit cards, most of the power and area is best used for cryptographic applications to make the transactions between the tag and the reader safer.
//Need for identification
Each tag would need an identification number to distinguish it from the others. It could be hard wired into the tag. For small groups of tags, this isn’t a significant over-head. But for tags like MBTA transit cards which may have many users, this could utilize a big chunk of the area resources.
//Need for True Random Number Generation
One cannot emphasize enough the need for secure keys for cryptography. Random numbers may be used to create challenges, padding bytes, and blinding values [x]
The longer the key is, the more time it takes for an attacker to guess it. But instead of brute forcing it, attackers exploit predictability in keys to break a system. TRNGs use the randomness of physical phenomena to generate truly random keys. Explored methods for creating on-chip TRNGs use additional amplifying or harvesting mechanism circuitry. This again, uses up expensive area and power.
//Using SRAM
There is a need for inexpensive identification or true random number generation on tags. A good way would be to use the existing resources without affecting their functionality. SRAM technology has been optimized for area and power. SRAM is available on-chip on some RFID tags. When powered off, the state of an SRAM cell is unknown. The SRAMs taken into consideration are cross coupled inverter based 6T SRAMs.
There are two types of SRAM cells:
1. Symmetric SRAM cells
In this case, both the inverters in an SRAM cell have gone through identical process variations, have similar threshold voltages and may initialize to a 0 or a 1 with equal probability on power-up. This is like flipping a coin, and the output is unpredictable on each power up. For several such cells in parallel, the output is an unpredictable binary stream. This output could be used as a true random number. It is different in each run.
2. Non-symmetric SRAM cells
In this case, the inverters in a cell differ from each other, such that one inverter triggers on before the other, nearly on every power-up. This may be because it’s threshold voltage is lower than the other’s. In this case the output is predictable every time and can serve as a fingerprint for that SRAM. It remains nearly constant through multiple runs.
//Working
To create fingerprint templates, the SRAM state is read on power-up multiple times. The bits that do not change much(*) across runs are identified as fingerprint bits. The bits that are unpredictable at each run are identified as TRNG bits. On field, the initial SRAM state is compared against the fingerprint templates using an efficient algorithm. This provides identification. The bit stream is then fed into a privacy amplifier, which produces a different output for even a bit-flip. This provides a true random number for a transaction.
//Conclusion
Thus the initial state of the SRAM can be used as a TRNG or a Fingerprint. Once the SRAM is read on power-up, it can be used for other purposes. There is little area overhead involved, and the power is obtained from powering up the SRAM.
//Concerns
Like any harvesting mechanism, the privacy amplifier may add correlation to the true random number.
//Pointers
Shrinking technology may cause more process variation due to spatially varying dopant concentrations and varying transistor gate sizes. Would this imply that SRAMs built on a smaller node would output more fingerprint bits than random bits…?